The present invention relates generally to broadband switching, and more particularly to fast reconfiguration of packet switching and asynchronous transfer mode (ATM) switching.
FIG. 1 shows a diagram of a conventional tree switch circuit 100. As shown, circuit 100 includes eight data inputs IN0-IN7. The use of eight inputs, however, is merely exemplary. In general, the number of inputs will be 2.sup.N, N being an integer greater than zero. Data inputs IN0-IN7 are received by a respective line of a plurality of data lines 110. Each line of data lines 110 is coupled to both 8.times.1 tree switch 120 and 8.times.1 tree switch 130 to couple data inputs IN0-IN7 to both tree switches as input signals. Tree switches 120 and 130 are the first and eighth tree switches of tree switch 100 with the intervening 8.times.1 tree switches omitted. Control inputs C0-C2 control tree switches 120 and 130 to produce data output signals OUT0 and OUT7, respectively, based on the input signals from data inputs IN0-IN7. The number of control inputs is equal to N.
Tree switches 120 and 130 each include N stages, N in this example being three, forming a cascade tree of seven 2:1 selectors, which are controlled by control inputs C0-C2. Stage #1 of tree switches 120 and 130 includes four 2:1 selectors, which are controlled by control input C0 to select four even (IN0, IN2, IN4, and IN6) or four odd numbered inputs (IN1, IN3, IN5, IN7). Similarly, stage #2 includes two 2:1 selectors, which are controlled by control input C1 to select two of the four outputs supplied by the four 2:1 selectors of stage #1. Finally, stage #3 includes one 2:1 selector, which is controlled by control input C2 to select one of the two outputs supplied by the two 2:1 selectors of stage #2. The outputs of the 2:1 selectors of stage #3 constitute the data output signals OUT0 and OUT7 of tree switches 120 and 130, respectively. Thus, the eight combinations of control inputs C0-C2 control tree switches 120 and 130 to pass any one of the eight data inputs IN0-IN7 to a particular data output.
Tree switch designs offer several advantages as compared to X-Y space switch architectures. For example, each selector stage of a tree structure drives only one input of the following stage, thereby minimizing the capacitive loading on the selector outputs, resulting in a high output bit-rate. In addition, in X-Y space switches, 2.sup.N inputs require 2.sup.N on-chip control lines. In a tree switch, however, 2.sup.N inputs only require N on-chip control lines, which eliminates on-chip decoders and minimized delay in the control path.
The following is an example of circuit 100 in operation. Assume that data input IN0 is coupled to data output OUT0, and data input IN7 is coupled to data output OUT7. From this initial setting, circuit 100 is to be reconfigured so that data input IN7 is coupled to data output OUT0, and data input IN0 is coupled to data output OUT7. Note that the bits of data inputs IN0-IN7 arrive in synchronization as input signals for tree switches 120 and 130 by a clock (not shown). The reconfiguration of circuit 100 includes a three-step process.
In the first step, circuit 100 waits until the last bit of data input IN0 has propagated through tree switch 120 to data output OUT0, and the last bit of data input IN7 has propagated through tree switch 130 to data output OUT0. Subsequently, the combinations of control inputs C0-C2 are altered for tree switches 120 and 130 to connect data input IN0 to data output OUT7 and data input IN7 to data output OUT0. During this alteration to reconfigure the connections between the data inputs and outputs, the paths through tree switches 120 and 130 for connecting the data inputs and outputs are indeterminate.
In the last step, after the path from data input IN0 to data output OUT0 has reached a stable disconnected state and the path from data input IN7 to data output OUT0 has reached a stable connected state, the first bit can be passed from data input IN7 to data output OUT0. Similarly, after reaching stable disconnected and connected states to OUT7, the first bit can be passed from data input IN0 to data output OUT7. Thus, in this process, although the control delay is minimized, the information flow to data outputs OUT0 and OUT7 must be stopped in order to allow for enough time to connect new data inputs to new data outputs.